Im totally confused by freertos Some port demos have /* The lowest priority. */
#define configKERNEL_INTERRUPT_PRIORITY 255
/* Priority 5, or 95 as only the top four bits are implemented. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 And some #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 255
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 191
#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15 /* The lowest priority. */
#define configKERNEL_INTERRUPT_PRIORITY configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 – configPRIO_BITS) )
/* Priority 5, or 95 as only the top four bits are implemented. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 – configPRIO_BITS) ) Why the two methods, what is the reasoning ?

History, and the weird way the Cortex-M defines interrupts. The Cortex-M has eight priority bits, but different implementations use a different number of bits.  Two things make this more confusing – first it is the most significant bits that are implemented and second high numeric values denote low logical priorities. Go right back to the beginning of the Cortex-M.  To define an interrupt priority you had to use all eight bits, and shift the values into the correct position (most significant bits).  Bits that are not use are normally set as 1 rather than 0 for “future proofing”. The next step – libraries start appearing for the Cortex-M early adopters.  These libraries want the priority specified as the raw value, that is the 8 bit shifted value. The next step – other libraries appear that want the priority defined as an eight bit value, but *not* shifted.  Now you have three ways of defining priorities. Finally CMSIS appears.  This wants priorities defined using just the implemented number of bits and not shifted. Therefore, the newer demos have more ways of defining the priorities than the older ports. configMAX_SYSCALL_INTERRUPT_PRIORITY and configLIBRARY_LOWEST_INTERRUPT_PRIORITY should always be equivalent, but the former is defined as if you are writing raw values to the Cortex-M3 NVIC registers and the latter is defined as if you are passing the value to a CMSIS (or propitiatory) library function that does the shifting for you. Confused.  You should be.  Stand on your head and half close your eyes, then Cortex-M interrupt priorities make sense. Regards.

Correction… configMAX_SYSCALL_INTERRUPT_PRIORITY should always be equivalent to configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY. Sorry – cut and paste the wrong constant out of the OP. Regards.

Hi Richard,
thanks for the overview. One of the reasons for posting was i’m struggling to get the OS to run with out it HardFaulting and thus i’m not sure about what the settings should be for the OS. Basically i have a UART which is interrput driven and it uses xQueueSendFromISR and xQueueRecieveISR. There are two queues used by these one TX and one RX. There is a task that sits waiting for the xQueueSendFromISR to put data into the queue and thus wakes up, but it only works for a small period of time. Or if i send alot of data to the RX of the UART from PC this also bombs it. Thus my I was just wanting to make sure ive got my interrupt priorities set duly. This is what ive currently got set. #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 11//5
#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15 /* The lowest priority. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 – configPRIO_BITS) )
/* Priority 5, or 95 as only the top four bits are implemented. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 – configPRIO_BITS) ) The UART interrupt is setup /* Enable the USART2 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_LOWEST_INTERRUPT_PRIORITY;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init( &NVIC_InitStructure ); NVIC is set to use all 4 bits
NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 ); KR

#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15

So configPRIO_BITS is 4 – which I think is correct for the STM32.

#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 11//5

So interrupts that use ISR safe FreeRTOS calls can use priorities 11, 12, 13 14 and 15.  Priorities above 11 never get disabled.

NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_LOWEST_INTERRUPT_PRIORITY;

Is this going into an ST propriatory function call?  I think so as it doesn’t look like a CMSIS function call.  I think it is right, from memory, but if you are having problems double check this expects the priorities passed in the least significant bits (which is what you are doing) and that the shifting to the most significant bits occurs inside the function. Other than that comments, I can’t see anything obviously wrong. Regards.

Hi Richard,
I have a similar problem with CAN interrupt and couldn’t figure out what is wrong.
Here is my code design: ///////CAN Receive interrupt////////////////////
{
    CAN_Receive(CAN1, CAN_FIFO0, &RxMsg);
    /***Do some processing on received message***/
   portBASE_TYPE xHigherPriorityTaskWoken = 0;
   xSemaphoreGiveFromISR(SEM_DEVICE_COMP_TASK_ID, &xHigherPriorityTaskWoken);
} //////Task waiting on semaphore////// – Task created using “xTaskCreate()” & priority set as “3”, Stack size as 128 bytes
{
   Wakes up this task and process received data & do a CAN Tx message which causes other node to send back another CAN message
} /////////////////CAN interrupt is set as follows///////////////
{
        NVIC_InitTypeDef  NVIC_InitStructure;
    NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_KERNEL_INTERRUPT_PRIORITY;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0;
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
    NVIC_Init(&NVIC_InitStructure);
} Also used NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 ); Used defaults settings for Freertos as below:
/* This is the raw value as per the Cortex-M3 NVIC.  Values can be 255
(lowest) to 0 (1?) (highest). */
#define configKERNEL_INTERRUPT_PRIORITY 255
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xb0, or priority 11. */ /* This is the value being used as per the ST library which permits 16
priority values, 0 to 15.  This must correspond to the
configKERNEL_INTERRUPT_PRIORITY setting.  Here 15 corresponds to the lowest
NVIC value of 255. */
#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15 In a slower message communication it works, but if I send lots of messages to STM32 it fails. It doesn’t receive all & CAN receive interrupt doesn’t work anymore. Ideally I want ISR to be completed & then run the task. Don’t want to interrupt ISR. Any help would be appreciated. Thanks,
SKV