- as per datasheet of hyperRAM , (S70KL1281 section 3.2Command/Address Bit Assignments ) , it takes several clock cycles to start data transfer .
- most importantly data bus of HyperRAM is of 8 bit & RTOS functionality is considering 32 bit ( as MCU is 32 bit ) . So data communication might not be ‘atomic’ .
Dear Support team, In one of the project we are planning to use FreeRTOS with external HyperRAM S70KL1281 ( http://www.cypress.com/file/183506/download ) with STM32L4R5ZI ( having Octal-SPI support https://www.st.com/content/ccc/resource/technical/document/application_note/group0/91/dd/af/52/e1/d3/48/8e/DM00407776/files/DM00407776.pdf/jcr:content/translations/en.DM00407776.pdf ) we need to execute all FreeRTOS functionality from FreeRTOS ( mainly heap memory ) But I have some basic doubts regarding context switching while communicating with External HyperRAM as follows:
I am not familiar with that particular combination, but here are my general observations: The datasheet says that the processor make the external memory look like internal memory, so that means that at the processor level, a request from the chip will processed a pull a bit from that memory into a local cache, transparently to the program. First, this means that you don’t need to worry about switching in the middle of a operation, the processor will handle the details itself. It does mean that you will get a slightly increased latency, as such a request will stall the processor (just like a request to other external memories, or sometimes even internal flash). Unless you have nano-second level latency requirements this probably isn’t a concern. Also, you don’t need to worry about the device being ‘8 bits’, the processor will grab enough data to do the operation.
Hi Richard Damon , Thanks for your reply . I will share results after getting assembled PCB with HyperRam , . Gaurav
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