As the cortex-M0 does not have a BASEPRI register, that means that interrupts can only be globally disabled through the PRIMASK register. But disabling through the PRIMASK register also means that most of the exceptions will be disabled including the SVC exception. The question is as an exclusive area needs interrupts to be globally disabled and inside this exclusive areas there is a usecase in which the SVCcall exception needs to be triggered, what would be the best way to go about doing just that? Are far as I have read , this is not architecturally possible. What can be done is to disable all the interrupts in the NVIC , but that would not be as efficient and can have other side effects and racing conditions.
Not looked for a little while – how would you disable all the interrupts in the NVIC without having to write to all the enable/disable registers? Would it be possible for you to pend an interrupt that executes after you are outside of the exclusive area rather than call SVC? If you are calling SVC from an exclusive area, and the SVC handler actually executed, you would need to keep it very short.
By setting the PRIMASK register, which disables the interrupts globally but also disables all the exceptions uptil level 0. Leaving only the reset handler and the Hardfault exception enabled. No I have to trigger a SVC call. Yes, the length of the handler is pretty short. The problem is the SVC handler cannot be triggered when the interrupts are globally disabled on the M0 using the PRIMASK register. Do you know of the top of your head how freertos handles exclusive areas on the M0?
If you know which interrupts are being used then you could replace the taskENTERCRITICAL() implementation with a macro that disables just those interrupts, and likes enables them again using taskEXITCRITICAL() – if the number of interrupts is small enough that might be practical but I don’t think disabling all interrupts would be fast enough.
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